Implementation conditions for delay insensitive circuits
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Designs of delay insensitive circuits must be proven correct in two different respects. First it must be demonstrated that a design meets its functional specification. Second it must be assured that it tolerates arbitrary delays in its individual components. The latter proof requires a model explicitly mentioning wire delays, whereas the former is much easier carried out in a model neglecting such delays
| # | Istituto/Sede | Collocazione | Inventario patrimoniale |
|---|---|---|---|
| Area della ricerca di Genova, Servizio di Documentazione Scientifica | Sede di Genova |
